DocumentCode :
58150
Title :
1-D Cell Generation With Printability Enhancement
Author :
Po-Hsun Wu ; Lin, Mark Po-Hung ; Tung-Chieh Chen ; Tsung-Yi Ho ; Yu-Chuan Chen ; Shun-Ren Siao ; Shu-Hung Lin
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Volume :
32
Issue :
3
fYear :
2013
fDate :
Mar-13
Firstpage :
419
Lastpage :
432
Abstract :
As process technologies advance to the subwavelength era, the 1-D design style is regarded as one of the most effective ways to continue scaling down the minimum feature size. To improve the printability of 1-D cell design, it is essential to insert dummy patterns and optimize line-end gap distribution for each layer. This paper presents novel 1-D cell generation algorithms that simultaneously minimize 1-D cell area and enhance the printability. Experimental results show that the proposed algorithms can effectively and efficiently reduce the number of diffusion gaps, minimize used routing tracks, insert sufficient dummy patterns, and eliminate stage-like line-end gaps without power and timing overhead. Consequently, the 1-D cell area is minimized and the printability of the cell is enhanced. To the best of our knowledge, this is also the first work in the literature that considers line-end gap distribution during 1-D cell generation.
Keywords :
integrated circuit design; lithography; 1D cell generation; 1D design style; line-end gap distribution optimization; lithography-aware cell generation; printability enhancement; Algorithm design and analysis; CMOS integrated circuits; Layout; MOS devices; Metals; Routing; Transistors; Cell generation; gridded design rule; printability enhancement; transistor placement and routing;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2012.2226454
Filename :
6461981
Link To Document :
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