An improved real-time hardware architecture for Canny edge detection based on FPGA

Edge detection is one of the key stages of image processing and object recognition. Canny edge detector is the most widely used edge detection algorithm because of its good performance. In this paper, a hardware architecture for real-time Canny edge detection has been proposed. By adopting the improved median filter, the performance and reliability of the system is improved when dealing with image contaminated by noise. A Shifting-LUT based direction calculation algorithm is adopted not only to improve the processing speed and reduce computational complexity but also to reduce the hardware consumption. The experimental results show that the hardware implementation is suitable for high performance and real-time applications.