Modeling and Performance Analysis of Network on Chip Based on Improved Asymmetric Multi-channel Router

Structure of the router has an enormous impact on performance of Network on Chip (NoC). Meanwhile, a fast and accurate performance analysis approach is extremely important for NoC early stage designs. In this paper, we propose an Improved Asymmetric Multi-Channel Structure (IAMCS) to promote the router performance. Then, we present its M/G/1/N queuing model for NoC performance analysis. With the proper value of m, it can efficiently reduce the average packet latency and increase the saturation throughput, and the mean relative error between the present model and simulation results is within 6.4%. For the NoC adopting IAMCS router, the proposed model can not only make accurate and efficient performance estimates, but also guide the design through optimization.