Low Power BIST for Scan-Shift and Capture Power

Low-power test technology has been investigated deeply to achieve an accurate and efficient testing. Although many sophisticated methods are proposed for scan-test, there are not so many for logic BIST because of its uncontrollable randomness. However, logic BIST currently becomes vital for system debug or field test. This paper proposes a novel low power BIST technology that reduces shift-power by eliminating the specified high-frequency parts of vectors and also reduces capture power. The authors show that the proposed technology not only reduces test power but also keeps test coverage with little loss.