Title :
Post-Silicon Jitter Measurements
Author :
Niitsu, Kiichi ; Yamaguchi, Takahiro J. ; Ishida, Masahiro ; Kobayashi, Haruo
Author_Institution :
Gunma Univ., Kiryu, Japan
Abstract :
This paper reviews the theory and introduces the architecture for a clock source with low phase noise and for measuring timing jitter. This approach utilizes a sample mean and sum of two random variables, and can be implemented in CMOS or SiGe BiCMOS circuits.
Keywords :
BiCMOS digital integrated circuits; clocks; timing jitter; BiCMOS circuit; clock source; low phase noise; post silicon jitter measurement; timing jitter measurement; Clocks; Phase frequency detector; Phase locked loops; Phase noise; Timing jitter; Voltage-controlled oscillators; bias error; cumulative distribution function; fail counter; histogram; probability density function; random error; random variable;
Conference_Titel :
Test Symposium (ATS), 2012 IEEE 21st Asian
Conference_Location :
Niigata
Print_ISBN :
978-1-4673-4555-2
Electronic_ISBN :
1081-7735
DOI :
10.1109/ATS.2012.15
