Title :
Invited talk: Noise and mismatch in sub 28nm silicon processes
Author :
Marshall, Andrew
Author_Institution :
Adv. CMOS Technol. Dev., Texas Instrum., Dallas, TX, USA
Abstract :
Mismatch and noise cause significant yield loss in 28nm and smaller process nodes. This paper examines these effects in analog, digital, RF and memory circuits, along with methods to quantify, account for and counteract problems associated with them.
Keywords :
CMOS analogue integrated circuits; CMOS memory circuits; elemental semiconductors; silicon; CMOS process; RF circuits; Si; analog circuits; digital circuits; memory circuits; process nodes; silicon process; size 28 nm; yield loss; Integrated circuit modeling; Logic gates; Mirrors; Noise; Noise measurement; Random access memory; Semiconductor process modeling;
Conference_Titel :
SOC Conference (SOCC), 2012 IEEE International
Conference_Location :
Niagara Falls, NY
Print_ISBN :
978-1-4673-1294-3
DOI :
10.1109/SOCC.2012.6398383
