Yield enhancement by logi-thermal simulation based testing

This paper proposes a method for yield enhancement in digital integrated circuit manufacture using a temperature dependent logic simulation tool. In an industrial environment the time slot dedicated to the logic testing of a single integrated circuit needs to be as short as possible in order to boost production. During this short period thermally induced errors might remain hidden due to long thermal time constants. This paper introduces a methodology to determine the steady-state die temperature where a short logic test is able to reveal logic faults. The evolved die temperature is simulated with a logi-thermal simulator engine that performs logic simulation by taking self-heating into account. We propose that the testing should take place at an elevated temperature where the temperature dependent failures arise. This approach makes it possible to detect otherwise hidden defects while keeping testing times short.