A 400-μW 3-GHz comparator in 65-nm CMOS

Author

Huynh, A.T. ; Sedighi, Behnam ; Duong, H.T. ; Le, Hung V. ; Skafidas, E.

Author_Institution

Nat. ICT Australia (NICTA), Univ. of Melbourne, Melbourne, VIC, Australia

fYear

2012

fDate

21-23 Nov. 2012

Firstpage

119

Lastpage

121

Abstract

This paper presents a high-speed clocked regenerative comparator designed in 65-nm CMOS process. The kickback noise caused by large variations at the regeneration nodes is suppressed using an intermediate stage. An extra switch is added between regeneration nodes to further equate their voltages when the comparator is at reset phase. The measured results show that the proposed comparator is able to achieve a Bit Error Rate (BER) of 2 × 10^-9 at a sensitivity of 12 mV at 1.4 GHz and 30 mV at 3 GHz. The power consumption of the proposed comparator is 75 μW at 500 MHz and 400 μW at 3 GHz.

Keywords

CMOS analogue integrated circuits; clocks; comparators (circuits); error statistics; field effect MMIC; CMOS process; bit error rate; frequency 1.4 GHz; frequency 3 GHz; frequency 500 MHz; high-speed clocked regenerative comparator; kickback noise; power 400 muW; power 75 muW; regeneration nodes; size 65 nm; voltage 12 mV; voltage 30 mV; Bit error rate; CMOS integrated circuits; Clocks; Inverters; Latches; Noise; Switches; Comparator; complementary metal-oxide-semiconductor(CMOS); high speed; kickback noise; offset;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio-Frequency Integration Technology (RFIT), 2012 IEEE International Symposium on

Conference_Location

Singapore

Print_ISBN

978-1-4673-2303-1

Type

conf

DOI

10.1109/RFIT.2012.6401633

Filename

6401633