DocumentCode
587723
Title
Lithography analysis of via-configurable transistor-array fabrics
Author
Dal Bem, Vinicius ; Reis, Andre I. ; Ribas, Renato P.
Author_Institution
Inst. of Inf., UFRGS, Porto Alegre, Brazil
fYear
2012
fDate
12-13 Nov. 2012
Firstpage
1
Lastpage
4
Abstract
Regular fabrics are expected to mitigate manufacturing process variations, increasing the fabrication yield in deep sub-micron CMOS technologies. This paper presents an extensive analysis of lithography behaviour of transistor-array based regular fabrics. Four different approaches presented in the literature (VCC, INVA, VCLB and VCTA) have been evaluated through lithography simulations. The well-established concept of edge placement error (EPE) has been taken into account as lithography behavior metric.
Keywords
CMOS integrated circuits; integrated circuit yield; lithography; transistors; deep sub-micron CMOS technology; edge placement error; fabrication yield; lithography analysis; manufacturing process variations; regular fabrics; via-configurable transistor-array fabrics; Computer architecture; Fabrics; Inspection; Integrated circuit modeling; Layout; Lithography; Very large scale integration; CMOS; Transistor array; digital IC design; fabrics; lithography simulation; via-configurable;
fLanguage
English
Publisher
ieee
Conference_Titel
NORCHIP, 2012
Conference_Location
Cpenhagen
Print_ISBN
978-1-4673-2221-8
Electronic_ISBN
978-1-4673-2222-5
Type
conf
DOI
10.1109/NORCHP.2012.6403145
Filename
6403145
Link To Document