Author :
Grenouillet, L. ; Khare, Priyank ; Gimbert, J. ; Hargrove, M. ; Jaud, M.A. ; Liu, Quanwei ; Le Tiec, Y. ; Wacquez, R. ; Loubet, N. ; Cheng, K. ; Holmes, Sam ; Liu, Siyuan ; Hook, T. ; Teehan, S. ; Guilford, J. ; Schmitz, S. ; Kulkarni, Parag ; Kuss, James
Abstract :
Planar fully depleted (FD) devices with thin Buried Oxide (BOX) offer the unique ability to incorporate effective back biasing which is a key enabler to build a versatile multi-Vt technology. From a dynamic standpoint, forward back bias lowers Vt and thus boost device performance, whereas reverse back bias increases Vt and thus decreases leakage. From a static point of view the back gate allows fine Vt tuning. Here we propose and evaluate a back gate implant scheme that enables a full use of the back bias.
Keywords :
MOSFET; circuit optimisation; silicon-on-insulator; FD devices; FDSOI transistors; NMOSFET; PMOSFET; back biasing; ground plane optimization; planar fully depleted devices; reverse back bias; size 20 nm; thin buried oxide; Boron; Current measurement; Doping; Implants; Logic gates; Silicon; Substrates;