Quasi-double gate mode for sleep transistors in UTBB FD SOI low-power high-speed applications

Power-gating enables low stand-by power for high-speed applications. In this paper, we exploit the unique feature of quasi-double gate (QDG) mode MOSFETs in UTBB SOI to boost the performances of the power-gating sleep transistor. According to experimental results on a 10-nm BOX, at nominal V_g QDG mode enables up to 35% width and thereby leakage reduction for the sleep transistor. At circuit level, a charge pump architecture is proposed to generate the QDG back-gate bias for a 100-mA power-gated CPU with sub-100 ns wake-up/sleep times and negligible power/area overheads.