6T SRAM design for wide voltage range in 28nm FDSOI

Author

Thomas, O. ; Zimmer, Bastian ; Pelloux-Prayer, B. ; Planes, N. ; Akyel, K.-C. ; Ciampolini, L. ; Flatresse, Philippe ; Nikolic, B.

fYear

2012

fDate

1-4 Oct. 2012

Firstpage

1

Lastpage

2

Abstract

Unique features of the 28nm ultra-thin body and buried oxide (UTBB) FDSOI technology enable the operation of SRAM in a wide voltage range. Minimum operating voltage limitations of a high-density (HD) 6-transistor (6T) SRAM can be overcome by using a single p-well (SPW) bitcell design in FDSOI. Transient simulations of dynamic failure metrics suggest that a HD 6T SPW array with 128 cells per bitline operates down to 0.65V in typical conditions with no assist techniques. In addition, a wide back-bias voltage range enables run-time tradeoffs between the low leakage current in the sleep mode and the short access time in the active mode, making it attractive for high-performance portable applications.

Keywords

SRAM chips; failure analysis; integrated circuit design; integrated circuit reliability; leakage currents; silicon-on-insulator; 6T SRAM design; HD 6T SPW array; SPW bit cell design; UTBB FDSOI technology; active mode; back-bias voltage range; dynamic failure metrics; high-density 6-transistor SRAM; high-performance portable applications; leakage current; single p-well bit cell design; size 28 nm; sleep mode; transient simulations; ultra-thin body and buried oxide FDSOI technology; voltage 0.65 V; Bit error rate; Clocks; High definition video; Leakage current; MOSFETs; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference (SOI), 2012 IEEE International

Conference_Location

NAPA, CA

ISSN

1078-621X

Print_ISBN

978-1-4673-2690-2

Electronic_ISBN

1078-621X

Type

conf

DOI

10.1109/SOI.2012.6404393

Filename

6404393