A Fast Configuration Technology of PCI Express Based on Partial Reconfiguration

PCI Express is a high-speed point-to-point transmission bus interface that widely used. but a standard PCI Express system starts to traversal the bus topology after 100ms from the power on and to make sure the equipment that ready to response the configuration request. This becomes a difficult task due to the ever-increasing configuration memory size of each new generation of FPGA, such as the Xilinx Virtex-6 family. in this paper, a two-step configuration method is proposed in order to solve the problem. a simulation result is also given in this paper.