Design of H.264 video encoder with C to RTL design tool

Author

Sangchul Kim ; Hyunjin Kim ; Taeil Chung ; Jin-Gyeong Kim

Author_Institution

SIC R&D Lab., LG Electron. Inc., Seoul, South Korea

fYear

2012

fDate

4-7 Nov. 2012

Firstpage

171

Lastpage

174

Abstract

In this, we present a design methodology to use C-to-RTL design tool for H.264 video encoder hardware design. We applied the HLS (High Level Synthesis) design methodology to design function blocks for H.264 video encoder IP. We give a comparison of a conventional RTL design methodology and the C-to-RTL design methodology in aspect of human resources and design time. We present how H.264 video encoder is designed using HLS design flow and how to improve verification method by reusing testbench for C level simulation and RTL simulation. We could develop H.264 SD and HD video encoder IP and embedded in DTV SoC successfully.

Keywords

C language; data compression; high level synthesis; logic circuits; logic design; system-on-chip; video coding; C level simulation; C-to-RTL design tool; DTV SoC; H.264 SD; H.264 video encoder design; HLS design flow; IP bock; high level synthesis design; human resources; testbench; verification method; Algorithm design and analysis; Design methodology; Encoding; Hardware; IP networks; Logic gates; Memory management; C-to-RTL; H.264; High-Level Synthesis; Multimedia IP design; Video Encoder;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2012 International

Conference_Location

Jeju Island

Print_ISBN

978-1-4673-2989-7

Electronic_ISBN

978-1-4673-2988-0

Type

conf

DOI

10.1109/ISOCC.2012.6407067

Filename

6407067