Modelling of high speed low power decoder in nanometer era

The advanced high performance and low leakage two in to four decoder are proposed in this paper. In order to reduce the power dissipation of CMOS products, at the time of digital circuits manufacturers required lower supply voltages and low power consumption. Leakage current in digital circuit is dominating factor, which is mainly affects the power consumption. We are compare the self controllable switch (SVL) with traditional CMOS technique in advance technology. After simulation we can see the result with the SVL technique is better than the traditional CMOS technique we can also reduced the leakage current and leakage power by self controllable switch(SVL) technique in two in to four decoder effectively. In this approach the effective voltage across digital circuits are reduced in inactive mode using a dynamic self controllable switch. Simulation result based on cadence tool.