Title :
A low power ASIP for precision configurable FFT processing
Author :
Yifan Bo ; Jun Han ; Yao Zou ; Xiaoyang Zeng
Author_Institution :
State-Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
Fast Fourier transformation (FFT) is a key operation in digital communication systems. Different communication standards require various FFT length and precision. In this paper, we present a low power Application-Specific Instruction-set Processor (ASIP) for variable length (16-point-4096-point) and bit precision (8-bit - 16-bit) to meet different requirements. We use scalable multipliers to construct the butterfly unit, which support both 8-bit and16-bit operation. The order of butterfly operation is adjusted to reduce twiddle-factorROM accesses, so as to reduce overall power consumption efficiently. Clock Gating is implemented to shut down processor´s pipeline during the FFT processin terms of special low power demands. Special Instructions are tailored to make full use of the flexible hardware.
Keywords :
body area networks; body sensor networks; clocks; fast Fourier transforms; instruction sets; medical computing; Clock Gating; butterfly unit; digital communication systems; fast Fourier transformation; flexible hardware; low power ASIP; low power application-specific instruction-set processor; power consumption; precision configurable FFT processing; twiddle-factor ROM accesses; word length 8 bit to 16 bit; Clocks; Computer architecture; Power demand; Radiation detectors; Read only memory; Wireless communication; Wireless sensor networks;
Conference_Titel :
Signal & Information Processing Association Annual Summit and Conference (APSIPA ASC), 2012 Asia-Pacific
Conference_Location :
Hollywood, CA
Print_ISBN :
978-1-4673-4863-8
