DocumentCode :
590816
Title :
Hardware architecture design of hybrid distributed video coding with frame level coding mode selection
Author :
Chieh-Chuan Chiu ; Hsin-Fang Wu ; Shao-Yi Chien ; Chia-Han Lee ; Somayazulu, V. Srinivasa ; Yen-Kuang Chen
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear :
2012
fDate :
3-6 Dec. 2012
Firstpage :
1
Lastpage :
4
Abstract :
Distributed video coding (DVC), a new video coding paradigm based on Slepian-Wolf and Wyner-Ziv theories, is a promising solution for implementing low-power and low-cost distributed wireless video sensors since most of the computation load is moved from the encoder to the decoder. In this paper, the hardware architecture design of an efficient distributed video coding system, hybrid DVC with frame-level coding mode selection, is proposed. With the fully block-pipelined architecture, coding mode pre-decision, and specially-designed LDPC code engine, the proposed hardware is an efficient solution for distributed video sensors with high rate-distortion performance.
Keywords :
parity check codes; video coding; wireless sensor networks; LDPC code engine; Slepian-Wolf theories; Wyner-Ziv theories; coding mode predecision; computation load; frame level coding mode selection; full block-pipelined architecture; hardware architecture design; high rate-distortion performance; hybrid DVC; hybrid distributed video coding; low-cost distributed wireless video sensors; Channel coding; Codecs; Hardware; Image coding; Quantization; Video coding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal & Information Processing Association Annual Summit and Conference (APSIPA ASC), 2012 Asia-Pacific
Conference_Location :
Hollywood, CA
Print_ISBN :
978-1-4673-4863-8
Type :
conf
Filename :
6411963
Link To Document :
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