An Efficient High Throughput FPGA Implementation of AES for Multi-gigabit Protocols

Due to the requirement of high throughput architecture for encrypted channels, an efficient implementation of hardware is needed. This can be achieved by using smart utilization of high end reconfigurable platforms. To achieve convincingly high throughput, an efficient non-pipelined style implementation of Advanced Encryption Standard (AES) with key size of 128-bit, for multigigabit protocols on Field Programmable Gate Array (FPGA)is presented.