STRAIGHT: Realizing a Lightweight Large Instruction Window by Using Eventually Consistent Distributed Registers

As the number of cores as well as the network size in a processor chip increases, the performance of each core is more critical for the improvement of the total chip performance. However, to improve the total chip performance, the performance per power or per unit area must be improved, making it difficult to adopt a conventional approach of super scalar extension. In this paper, we explore a new core structure that is suitable for many core processors. We revisit prior studies of new instruction level (ILP) and thread-level parallelism (TLP) architectures and propose our novel STRAIGHT processor architecture. By introducing the scheme of distributed key-value-store to the register file of clustered micro architectures, STRAIGHT directly executes the operation with large logical registers, which are written only once. By discussing the processor structure, micro architecture, and code model, we show that STRAIGHT realizes both large instruction window and lightweight rapid execution, while suppressing the hardware and energy cost. Preliminary estimation results are promising, and show that STRAIGHT improves the single thread performance by about 30%, which is the geometric mean of the SPEC CPU 2006 benchmark suite, without significantly increasing the power and area budget.