Distributed arithmetic multiplier based Artificial Neural Network architecture for image compression

In this paper we present FPGA implementation of Artificial Neural Networks for image compression. Image compression is a process which minimizes the size of an image file to an unacceptable level without degrading the quality of the image. The main components of an artificial neuron are adders and multipliers. In order to implement neural network, large number of adders and multipliers are required. The main constraint in the implementation of neural network is the area occupied by the multipliers. In order to overcome this area we propose the use of constant coefficient multiplier like distributed arithmetic (DA) based multiplier. The area efficiency is obtained by use of adders and shifters in Distributed arithmetic based multiplier architecture. The distributed arithmetic based multiplier is made use to implement 4:4:2:2:4 and 16:16:8:8:16 artificial neural network architecture for image compression. These architectures are implemented on FPGA and area efficiency is obtained.