A systolic-based architecture for a novel reduced-complexity GPS receiver

In this paper, a novel structure of GPS receiver is proposed. The considered GPS acquisition system leverages a systolic-based array structure of regular and simple locally-connected processing-elements (PEs). The new GPS scheme is simulated and its complexity is evaluated for a real-time implementation on a field programmable gate array (FPGA). The suggested systolic-based acquisition system promises high performance for GPS receivers by yielding greatly improved processing latency and estimation precision while offering an efficient and flexible implementation of a significantly reduced complexity of a fully pipelined architecture.