DocumentCode
59576
Title
Digitally tuned degeneration resistance to improve linearity of boost factors for analogue equalisers
Author
Zinan Wang ; Weixin Gai
Author_Institution
Inst. of Microelectron., Peking Univ., Beijing, China
Volume
51
Issue
10
fYear
2015
fDate
5 14 2015
Firstpage
745
Lastpage
747
Abstract
An analogue equaliser with a novel digitally tuned variable degeneration resistance is realised in a 65 nm CMOS technology. Implemented with three parallel resistance branches and one serial resistance branch to well fit the optimal conductance curve, the proposed variable degeneration resistance is exploited to achieve a wide boost range while significantly improving the linearity of the tuned boost factors compared with the equaliser with a traditional degeneration resistance structure.
Keywords
CMOS analogue integrated circuits; electric resistance; equalisers; CMOS technology; analogue equalisers; boost factors; digitally tuned degeneration resistance; linearity; optimal conductance curve; parallel resistance branches; serial resistance branch; size 65 nm; wide boost range;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el.2015.0461
Filename
7105456
Link To Document