Energy-efficient multi-task computing on MPSoCs: A case study from a memory perspective

To support growing data rates under low-power constraints, personal mobile devices rely on multi-core architectures which are challenged by increasing energy efficiency requirements. A mobile device is essentially a combination of two subsystems (a “PC” and a “radio”), which are often implemented as distinct multiprocessor systems-on-chip (MPSoC). The former supports multimedia processing and implements the end-user interface by relying on multi-thread computing under the management of a conventional operating system; the latter implements baseband processing by performing multi-task computing under the management of a real-time operating system. This paper focuses on the latter subsystem by describing a case study that estimates, from a memory perspective, the evolution of the energy efficiency for periodic multi-task computing as process technologies improve (90nm, 65nm, 45nm, and 32nm). The results show that real-time schedulability requirements limit the growth of throughput with increasing cache size in such a way that the extra cache consumption does not pay off. They also show that, in the context of multi-task computing, more than 89% of the energy spent in the memory subsystem is due to dynamic consumption. Such results allowed us to identify crucial cache optimizations to cope with increasing energy efficiency requirements.