• DocumentCode
    596943
  • Title

    Decoder for an enhanced serial generalized bit flipping algorithm

  • Author

    Garcia-Herrero, Francisco ; Canet, Maria Jose ; Valls, Javier

  • Author_Institution
    Inst. de Telecomun. y Aplic. Multimedia, Univ. Politec. de Valencia, Gandia, Spain
  • fYear
    2012
  • fDate
    9-12 Dec. 2012
  • Firstpage
    412
  • Lastpage
    415
  • Abstract
    An enhanced serial generalized bit-flipping algorithm is proposed in this paper. This new algorithm includes method to compute the extrinsic information during all the iterations, improving the performance of the algorithm in the waterfall region compared to the direct serial description. In addition, the algorithm allow us to reduce the storage resources the derived architecture. The decoder was implemented on a Virtex-VI FPGA device for the (837,723) non-binary code over GF(25), achieving 439 Mbps at 10 iterations.
  • Keywords
    decoding; field programmable gate arrays; Virtex-VI FPGA device; decoder; direct serial description; enhanced serial generalized bit flipping algorithm; nonbinary code; waterfall region; Clocks; Computer architecture; Decoding; Parity check codes; Proposals; Random access memory; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on
  • Conference_Location
    Seville
  • Print_ISBN
    978-1-4673-1261-5
  • Electronic_ISBN
    978-1-4673-1259-2
  • Type

    conf

  • DOI
    10.1109/ICECS.2012.6463662
  • Filename
    6463662
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=596943