Fully-parallel LUT-based (2048,1723) LDPC code decoder for FPGA

Author

Torres, V. ; Perez-Pascual, A. ; Sansaloni, T. ; Valls, Javier

Author_Institution

Inst. de Telecomun. y Aplic. Multimedia, Univ. Politec. de Valencia, Valencia, Spain

fYear

2012

fDate

9-12 Dec. 2012

Firstpage

408

Lastpage

411

Abstract

A good trade-off between performance and complexity is achieved if the min-sum algorithm with 2-bit non-uniform quantization is used to decode Low-Density Parity-Check codes. This paper proposes a method to design Variable Node Update (VNU) units based on Look-up tables suitable to design decoders for this algorithm. The method has been developed for the (2048,1723) LDPC code of the IEEE 802.3an standard and fully-parallel architectures have been implemented in a FPGA device. The results show that with the proposed method 35% area saving is achieved with respect to the use of the conventional VNU units.

Keywords

decoding; field programmable gate arrays; parallel architectures; parity check codes; quantisation (signal); table lookup; FPGA device; IEEE 802.3an standard; VNU unit; decoder design; fully-parallel LUT-based LDPC code decoder; fully-parallel architecture; look-up table; low-density parity-check code; min-sum algorithm; nonuniform quantization; variable node update; word length 2 bit; Algorithm design and analysis; Decoding; Field programmable gate arrays; Iterative decoding; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on

Conference_Location

Seville

Print_ISBN

978-1-4673-1261-5

Electronic_ISBN

978-1-4673-1259-2

Type

conf

DOI

10.1109/ICECS.2012.6463663

Filename

6463663