• DocumentCode
    596965
  • Title

    A redundant wire addition method for Patchable Accelerator

  • Author

    Wakizaka, M. ; Yoshida, Hiroyuki ; Hara-Azumi, Y. ; Yamashita, Shinji

  • Author_Institution
    Ritsumeikan Univ., Kusatsu, Japan
  • fYear
    2012
  • fDate
    9-12 Dec. 2012
  • Firstpage
    552
  • Lastpage
    555
  • Abstract
    Patchable Accelerator has been recently proposed to achieve high frequency and high energy-efficiency with enabling post-silicon Engineering Change (EC). However, Patchable Accelerator suffers from too much usage of the hardware resources when an EC takes place. In addition, Patchable Accelerator needs to delay operations to deal with ECs under some specific conditions. These problems occur because of lack of wires. Therefore, we propose a heuristic method such that redundant wires are added to the most appropriate parts in a datapath. Our case study shows that our method is much quicker than a brute-force approach and its result is near optimum.
  • Keywords
    integrated circuit design; wires (electric); heuristic method; patchable accelerator; post-silicon engineering change; redundant wire addition method; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on
  • Conference_Location
    Seville
  • Print_ISBN
    978-1-4673-1261-5
  • Electronic_ISBN
    978-1-4673-1259-2
  • Type

    conf

  • DOI
    10.1109/ICECS.2012.6463687
  • Filename
    6463687