DocumentCode
597006
Title
On the design of a 2-2-0 MASH delta-sigma-pipeline modulator
Author
Mohammadi, Reza ; Shamsi, H. ; Abedinkhan, M.
Author_Institution
Fac. of ECE, K.N. Toosi Univ. of Technol., Tehran, Iran
fYear
2012
fDate
9-12 Dec. 2012
Firstpage
348
Lastpage
351
Abstract
In this paper, a 2-2-0 MASH delta-sigma modulator is presented. This architecture consists of two single-bit second-order delta-sigma modulators in the first and second stages and a pipeline ADC in the last stage. In the conventional cascaded delta-sigma-pipeline modulators, consisting of a single-loop delta-sigma modulator at the first stage and a pipeline ADC at the second stage, in order to achieve higher order noise shaping and stability of the modulator simultaneously, multi-bit quantizer and multi-bit DAC must be used, which cause the DAC non-linearity problem. Implementation of the cascaded delta-sigma-pipeline structure on a single bit 2-2 MASH delta-sigma modulator is proposed in this work and its advantages and disadvantages are considered in detail. The key feature of the proposed modulator is taking the advantages of 2-2 MASH delta-sigma modulator compared to other conventional cascaded delta-sigma-pipeline modulators. This architecture offers the possibility of implementation of a power efficient, fourth-order cascaded delta-sigma-pipeline modulator without having the stability or DAC non-linearity problems. The mismatch between the digital and analog filters in the pipeline part is also shaped by the order of two and therefore its hazardous effects are reduced. The system level simulation using MATLAB/SIMULINK confirms the usefulness of the presented structure.
Keywords
analogue-digital conversion; delta-sigma modulation; digital filters; modulators; 2-2-0 MASH delta-sigma-pipeline modulator design; DAC nonlinearity problem; MATLAB/SIMULINK; analog filter; cascaded delta-sigma-pipeline structure; digital filter; fourth-order cascaded delta-sigma-pipeline modulator; higher order noise shaping; modulator stability; multibit DAC; multibit quantizer; pipeline ADC; single-bit second-order delta-sigma modulator; single-loop delta-sigma modulator; system level simulation; Digital filters; Modulation; Multi-stage noise shaping; Pipelines; Signal to noise ratio; Transfer functions;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on
Conference_Location
Seville
Print_ISBN
978-1-4673-1261-5
Electronic_ISBN
978-1-4673-1259-2
Type
conf
DOI
10.1109/ICECS.2012.6463730
Filename
6463730
Link To Document