DocumentCode
597022
Title
A template for the construction of efficient checkers with full verification guarantees
Author
Freitas, L.S. ; Andrade, G.A.G. ; dos Santos, Luiz C. V.
Author_Institution
Fed. Univ. of Santa Catarina, Florianópolis, Brazil
fYear
2012
fDate
9-12 Dec. 2012
Firstpage
280
Lastpage
283
Abstract
To overcome the burden of high-latency operations, system designers often resort to relaxed specifications, which allow multiple outstanding operations to be concluded out of their issuing order. Because conventional scoreboards assume in-order responses, they often rely on heuristics or time-domain synchronization to mitigate their inherent limitation. However, such expedients might result in false positives (or negatives), affecting both the checker´s effort and effectiveness. By relying on established guarantees for postmortem checkers, this paper proves that relaxed scoreboards can be built with full verification guarantees, as far as they employ an update rule based on the removal of dominators. Experimental results show that a well-designed relaxed scoreboard needs approximately 1/2 of the effort required by a conventional one.
Keywords
integrated circuit design; time-domain analysis; high-latency operation; postmortem checker; relaxed specification; scoreboard; system designer; time-domain synchronization; Bipartite graph; Computers; Out of order; Protocols; Runtime; Synchronization; Time domain analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on
Conference_Location
Seville
Print_ISBN
978-1-4673-1261-5
Electronic_ISBN
978-1-4673-1259-2
Type
conf
DOI
10.1109/ICECS.2012.6463746
Filename
6463746
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