Title :
3DIC stacked system technology and application
Author :
Yi-Jen Chan ; Wei-Chung Lo
Author_Institution :
Electron. & Optoelectron. Res. Labs., Ind. Technol. Res. Inst. (ITRI), Hsinchu, Taiwan
fDate :
Oct. 29 2012-Nov. 1 2012
Abstract :
A target 3D stacked system consists of two or more layers/building blocks through the horizontal or vertical interconnects to integrate different functional circuitries into one single circuit. By adopting through Silicon Via(TSV) formation, thin wafer handling, fine-pitch micro-joints, chip-to-wafer(C2W), and wafer-to-wafer(W2W) technologies, this single-circuit stacked system can perform SoC-like or even better performance with lower power and higher bandwidth. In this paper, the benefits of stacked system, opportunities, challenges and perspective of 3D integrations are discussed as well as ITRI´s roadmaps and recent technology achievement are presented. Finally, the future potential application and emerging worldwide value chain and business model of 3D stacked system are proposed.
Keywords :
integrated circuit interconnections; system-on-chip; three-dimensional integrated circuits; 3DIC stacked system technology; C2W technology; ITRI roadmap; SoC; TSV formation; W2W technology; chip-to-wafer technology; fine-pitch microjoint; horizontal interconnection; layer-building block; single-circuit stacked system; thin wafer handling; through silicon via formation; vertical interconnection; wafer-to-wafer technology; Bonding; Silicon; Solid modeling; Stacking; Through-silicon vias; Tin;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-2474-8
DOI :
10.1109/ICSICT.2012.6467674