Design of anti-radiation CMOS pixel on SOI wafer

As the demand grows for applications of higher reliability, the industry pushes for CMOS image sensors that deliver better anti-radiation performance. The SOI technology (Silicon-On-Insulator), widely-known as the best solution so far, in this regard, introduces a buried oxide layer in between the top silicon layer and the sub one. Isolating devices apart from the substrate, the buried oxide layer is able to effectively cut out the influence of electron-hole pairs that are generated by the radiation. However, a traditional SOI wafer has such a thin top silicon layer (usually less than 100nm in thickness) that when it is applied to CMOS image sensors, pixels lack the desirable depth to absorb the long wavelength light. Thereby, we designed a new type of pixel, simulated it in TCAD software, and noted the result was satisfactory.