The effect of LUT size on nanometer FPGA architecture

In this paper, the effect of the LUT size on the FPGA area and delay with the recent progress of the semiconductor technology is investigated. An optimized routing area and delay modelling in FPGA architecture with nanometer process is proposed. The proposed method has advantage on accuracy over the previous modelling, due to different spacings for nanometer process. With the improved modelling, we determine the best LUT size in terms of FPGA area and delay by a CAD flow including ABC, Hspice, T-Vpack and VPR. The experimental results show that 6-LUT provides the best area-delay product for a nanometer FPGA.