Greedy algorithm based XNOR/OR gates decomposition

Decomposition of multi-input gates is indispensable to low power optimization of Reed-Muller (RM) logic circuits, which also has a direct impact on the power dissipation of the final circuits. The commonly used decomposition method based on classification is analyzed, and a heuristic algorithm based on greedy technique is proposed for XNOR/OR circuit decomposition, which aims at lowering circuits´ power. The proposed algorithm is tested by MCNC Benchmarks and the simulation results indicate that the proposed decomposition is more likely to lead to lower power circuits than the classification based one.