DocumentCode
598394
Title
An innovative sensing architecture for multilevel Flash memory
Author
Xiao-Min Gao ; Yuan Wang ; Yan-Dong He ; Gang-Gang Zhang ; Xing Zhang
Author_Institution
Key Lab. of Microelectron. Devices & Circuits (MoE), Peking Univ., Beijing, China
fYear
2012
fDate
Oct. 29 2012-Nov. 1 2012
Firstpage
1
Lastpage
3
Abstract
Multilevel cell storage allows two or more bits to be stored in one cell, thus reducing almost 50% of Flash memory´s area without technology shrinkage. Basic concepts like sensing schemes in multilevel Flash memory are fundamental and need further research. In this paper, an innovative sensing architecture is presented, with the name of serial-parallel sensing scheme, which provides fast read speed and a medium area cost and power consumption, compared with conventional parallel and serial sensing schemes. Using 65nm technology, the new architecture performs well, almost five times as fast as serial sensing and has advantage over parallel sensing in both area and power consumption cost.
Keywords
CMOS integrated circuits; amplifiers; flash memories; innovative sensing architecture; multilevel cell storage; multilevel flash memory; parallel sensing; sensing amplifiers; serial sensing; size 65 nm; technology shrinkage; Capacitors; Computer architecture; Flash memory; Microprocessors; Power demand; Sensors; Transistors; Multilevel storage; sensing amplifier; serial-parallel sensing architecture;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location
Xi´an
Print_ISBN
978-1-4673-2474-8
Type
conf
DOI
10.1109/ICSICT.2012.6467797
Filename
6467797
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