Fast-locking phase-error compensation technique in PLL

This work represents a phase-locked loop (PLL) which has fast locking time. The proposed phase-error compensation technique is conducted by delay cells and switches used for compensating phase-error during frequency hop. And a conventional digital discriminator aided phase detector (DAPD) is used for lock detector. The DAPD continuously detects the phase difference and enlarges the bandwidth of PLL by changing the charge pump currents, loop filter. During the frequency tracking with wide bandwidth, phase-error compensation block adjust the delay of output of programmable divider by the polarity of phase-error The proposed technique is incorporated in the design of a 1.55-GHz PLL. Simulated in the Dongbu 0.11-μm CMOS technology, the whole PLL dissipates 0.97 mW from 1.2-V supply. The measured settling time, 1.5-μs, is improved compared to bandwidth switching technique.