Numerical simulation of polysilicon TFTs based on discrete grain boundaries

Author

Wan-Ling Deng ; Jun-Kai Huang ; Jin He ; Hong-Yu He

Author_Institution

Dept. of Electron. Eng., Jinan Univ., Guangzhou, China

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

Numerical simulations of grain boundaries barriers and drain current are carried out in polysilicon thin-film transistors based on discrete grain boundaries (GBs). The height of grain boundary barrier was analyzed under various biases conditions and drain induced grain barrier lowering (DIGBL) effect was observed. The influence of trap states density in GBs on current characteristics was also studied and simulated. The transfer characteristics with various drain-to-source voltages are demonstrated.

Keywords

elemental semiconductors; grain boundaries; numerical analysis; silicon; thin film transistors; Si; discrete grain boundary barrier; drain current; drain induced grain barrier lowering effect; drain-to-source voltage; numerical simulation; polysilicon TFT; polysilicon thin-film transistor; transfer characteristics; trap state density; Electric potential; Grain boundaries; Integrated circuit modeling; Logic gates; Numerical models; Numerical simulation; Thin film transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6467840

Filename

6467840