A PVT insensitive BCT circuit with replica calibration for high speed charge-domain pipelined ADCs

Author

Shuang Zhu ; Hong Zhang ; Xue Li ; Dong Li ; Zhenhai Chen ; Jun Cheng

Author_Institution

Sch. of Electron. & Inf. Eng., Xi´an Jiaotong Univ., Xi´an, China

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

A boosted charge transfer (BCT) circuit with replica calibration for high-speed charge domain (CD) pipelined analog to digital converters (ADCs) is presented in this paper. The common-mode charge errors caused by PVT variations can be rejected by the negative feedback network inside the replica circuit of the BCT. A 250-MSPS, 10bit CD pipelined ADC based on the proposed BCT achieves a SNDR of 56.7dB without digital calibration. The ADC is fabricated with SMC 0.18 μm CMOS process and consumes 150mW from a 1.8V power supply.

Keywords

CMOS integrated circuits; analogue-digital conversion; calibration; charge exchange; circuit feedback; integrated circuit design; integrated circuit measurement; CD; PVT insensitive BCT circuit; analog to digital converter; boosted charge transfer circuit; common-mode charge error; high speed charge-domain pipelined ADC; negative feedback network; noise figure 56.7 dB; power 150 mW; process-supply voltage-temperature variation; replica calibration; size 0.18 mum; voltage 1.8 V; word length 10 bit; Accuracy; Calibration; Charge transfer; Clocks; Pipelines; Power supplies; Temperature measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6467897

Filename

6467897