Title :
Within ESD Bus Resistance — A new scaling issue
Author_Institution :
Dr. Steven H. Voldman LLC, South Burlington, VT, USA
fDate :
Oct. 29 2012-Nov. 1 2012
Abstract :
A new metric, “Within ESD Bus Resistance” - a limitation on the ESD results due to power bus scaling, will be demonstrated with voltage drop simulation, failure analysis, SEM cross sections, HBM and MM ESD test results, and a novel ESD “resistance shunt” solution is demonstrated.
Keywords :
application specific integrated circuits; electric potential; electrostatic discharge; failure analysis; integrated circuit design; integrated circuit interconnections; integrated circuit reliability; integrated circuit testing; scaling circuits; scanning electron microscopy; ASIC interconnection; ESD bus resistance shunt; HBM; MM; SEM cross section; failure analysis; power bus scaling; voltage drop simulation; Clamps; Current distribution; Electrostatic discharges; Failure analysis; Immune system; Resistance;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-2474-8
DOI :
10.1109/ICSICT.2012.6467918
