An accurate dynamic power model on FPGA routing resources

Accurately modeling the dynamic power of FPGAs is a challenging task due to the changeable functionality and a large number of pass transistors. These two terms cannot be accurately described by the conventional power modeling techniques for ASICs. In this paper, a novel power model for FPGA is proposed considering both pass transistors and MUXes, two major components of FPGA routing resources. A novel power model for the pass transistor is developed considering the varying input and output voltages, which highly improves the accuracy in power estimation. The average error in dynamic power for pass transistor chains and MUXes is below 3% and 5%, respectively, as compared to HSPICE simulations.