DocumentCode :
598761
Title :
3D simulation of substrate noise coupling from Through Silicon Via (TSV) and noise isolation methods
Author :
Lin, Leo Jyun-Hong ; Hsiao-Pu Chang ; Tzong-Lin Wu ; Yih-Peng Chiou
Author_Institution :
Grad. Inst. of Photonics & Optoelectron., Nat. Taiwan Univ., Taipei, Taiwan
fYear :
2012
fDate :
9-11 Dec. 2012
Firstpage :
181
Lastpage :
184
Abstract :
This paper presents simulation results of substrate noise coupling between through silicon via (TSV) and MOSFET. Electrical noise coupling through coexistence of junction capacitances and threshold modulation in substrate is studied and discussed through 2D and 3D transient analyses in this paper. Furthermore, noise isolation methods including guard rings and grounded shield TSV are incorporated to improve the noise decoupling and are examined to verify their effectiveness.
Keywords :
MOSFET; circuit simulation; integrated circuit noise; three-dimensional integrated circuits; transient analysis; 2D transient analysis; 3D simulation; 3D transient analysis; MOSFET; electrical noise coupling; grounded shield TSV; guard rings; junction capacitances; noise decoupling; noise isolation methods; substrate noise coupling; threshold modulation; through silicon via; Noise; Semiconductor process modeling; Substrates; Switches; Through-silicon via (TSV); noise isolation; substrate noise coupling; transient analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2012 IEEE
Conference_Location :
Taipei
Print_ISBN :
978-1-4673-1444-2
Electronic_ISBN :
978-1-4673-1445-9
Type :
conf
DOI :
10.1109/EDAPS.2012.6469415
Filename :
6469415
Link To Document :
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