Deep experimental investigation of NBTI impact on CMOS inverter reliability

Negative Bias Temperature Instability has become a major reliability concern in CMOS circuits. This is due to the fact that PMOS transistors of these circuits are submitted to many parameters shifts resulting in circuit performance degradations. In order to mitigate NBTI, IC designers need to accurately evaluate the NBTI induced performance degradations of their circuits to conduct aging simulation of their circuit lifetime. For this purpose, we present in this work a deep experimental investigation of NBTI impact on the CMOS inverter. The experimental setup of the DC NBTI has been conducted by Measure Stress Measure Method where a set of Negative stress Voltages at different temperatures were continuously applied for duration of 3600s. The results show that NBTI does shift the inverter´s Voltage Transfer Curve, decreases its logic threshold, unbalance its logic states, and degrades its noise immunity. The obtained results demonstrate that these degradations worsen with both high negative stress voltage and elevated temperature and consequently impact the CMOS inverter robustness and thus its reliability.