Radiation-Hardening Technique for Voltage Reference Circuit in a Standard 130 nm CMOS Technology

Author

Piccin, Yohan ; Lapuyade, Herve ; Deval, Yann ; Morche, Colette ; Seyler, Jean-Yves ; Goutti, Frederic

Author_Institution

IMS Lab., Talence, France

Volume

61

Issue

2

fYear

2014

fDate

Apr-14

Firstpage

967

Lastpage

974

Abstract

A radiation-hardening technique for a CMOS voltage reference circuit is proposed. Its operation principle consists in combining linearly two different NMOS threshold voltages and a Proportional-To-Absolute-Temperature (PTAT) voltage, which allows the compensation of both temperature-induced and radiation-induced discrepancies. This circuit was implemented in a standard 130 nm CMOS technology and designed in two different layouts. Measurements show a good operation with a minimal supply voltage of 2.5 V, a PSRR of 80 dB at 3.3 V. The voltage output shift is around 0.5% under irradiation up to 40 krad(Si). The active area of the circuit is about 0.04 mm².

Keywords

CMOS integrated circuits; integrated circuit layout; radiation hardening; reference circuits; NMOS threshold voltages; proportional-to-absolute-temperature voltage; radiation-hardening technique; size 130 nm; standard 130 nm CMOS technology; voltage 3.3 kV; voltage output shift; voltage reference circuit; CMOS integrated circuits; CMOS technology; Layout; Logic gates; MOSFET; Threshold voltage; Dose; interface-trap charge; oxide-trap charge; radiation; threshold-voltage;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2014.2312269

Filename

6782277