DocumentCode
599779
Title
Mathematical modelling of accumulation layer thickness of fully depleted G4-FETs
Author
Sayed, Shehrin ; Khan, M. Ziaur Rahman
Author_Institution
Dept. of Electr. & Electron. Eng., Bangladesh Univ. of Eng. & Technol., Dhaka, Bangladesh
fYear
2012
fDate
20-22 Dec. 2012
Firstpage
795
Lastpage
798
Abstract
A physics based mathematical model is proposed here to determine the accumulation layer thickness in thin film fully depleted G4-FETs. The model was derived as a function of surface potential which was calculated by self-consistently solving two dimensional Poisson´s equation. The dependence of accumulation layer thickness on gate biases as well as the device structural parameters are also analysed here. The purpose of proposing this model is to determine the range of structural parameters for designing the devices, within which the accumulation layer thickness remains small enough to be approximated as a sheet of charge of zero thickness so that popular charge sheet model can be used to analyse transistor characteristics. Moreover, the biasing range can be determined also for which charge-sheet model can be used to design circuits.
Keywords
MOSFET; Poisson equation; accumulation layers; silicon-on-insulator; accumulation layer thickness; accumulation-mode SOI MOSFET; charge sheet model; circuit design; device structural parameters; gate biases; physics based mathematical model; silicon-on-insulator; surface potential function; thin film fully depleted G4-FET; transistor characteristics; two dimensional Poisson equation; zero thickness; Electric potential; Films; Integrated circuit modeling; Logic gates; Mathematical model; Silicon; Transistors; Accumulation Layer Thickness; Charge-Sheet Model; Fully Depleted G4-FET;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical & Computer Engineering (ICECE), 2012 7th International Conference on
Conference_Location
Dhaka
Print_ISBN
978-1-4673-1434-3
Type
conf
DOI
10.1109/ICECE.2012.6471670
Filename
6471670
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