• DocumentCode
    599782
  • Title

    Analytical modeling of the SOI four-gate transistor using conformal mapping

  • Author

    Snigdha, F.S. ; Bappy, Mehedy Hasan ; Sultana, N. ; Shuvra, S.R. ; Chowdhury, T.T. ; Khan, M. Ziaur Rahman

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Bangladesh Univ. Of Eng. & Technol., Dhaka, Bangladesh
  • fYear
    2012
  • fDate
    20-22 Dec. 2012
  • Firstpage
    806
  • Lastpage
    809
  • Abstract
    Conformal mapping technique is used to model potential distribution of SOI four gate transistor in sub threshold region. The modeling is based on the solution of Laplace´s equation. Potential variation between the lateral junction-gates is assumed to be parabolic. The potential variation between the MOS gates and junction gates are also studied for different structural parameters.
  • Keywords
    Laplace equations; MOSFET; conformal mapping; silicon-on-insulator; G4-FET; Laplace equation; MOS gates; MOSFET; SOI four-gate transistor; analytical modeling; conformal mapping technique; lateral junction gates; silicon-on-insulator; structural parameters; subthreshold region; Conformal mapping; Electric potential; Junctions; Laplace equations; Logic gates; Mathematical model; Transistors; G4FET; conformal mapping; surface potential;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical & Computer Engineering (ICECE), 2012 7th International Conference on
  • Conference_Location
    Dhaka
  • Print_ISBN
    978-1-4673-1434-3
  • Type

    conf

  • DOI
    10.1109/ICECE.2012.6471673
  • Filename
    6471673
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=599782