Resource efficient and area optimized Gr⊘stl implementation on FPGA

Author

Adnan, Syed Muhammad ; Aziz, Ahmedullah

Author_Institution

Dept. of Electr. Eng., Nat. Univ. of Sci. & Technol., Islamabad, Pakistan

fYear

2012

fDate

20-22 Dec. 2012

Firstpage

1

Lastpage

4

Abstract

SHA-3 is the next family of cryptographic hash algorithms. The purpose to develop SHA-3 is to remove the vulnerabilities of SHA-1 and SHA-2. This paper implements Grostl hash algorithm on FPGA, which was among the five finalists of the competition. This work focuses on low area implementation of Grostl for optimum throughput to area ratio (TPA). For this purpose fully autonomous interleaved design architecture is used. Interleaved design executes permutations P and Q serially one after another. Interleaved design is implemented with two approaches one using Distributed Memory and the other using Block Memory. The post place and route results obtained on virtex-6 are throughput 6844Mbits/s, occupied slices 1470 and TPA 4.65.

Keywords

cryptography; distributed memory systems; field programmable gate arrays; FPGA; Grøstl hash algorithm; SHA-1; SHA-2; SHA-3; TPA; area optimized Grøstl implementation; autonomous interleaved design architecture; block memory; cryptographic hash algorithms; distributed memory; permutations; resource efficient implementation; throughput to area ratio; virtex-6; Cryptography; Educational institutions; Field programmable gate arrays; Memory architecture; Random access memory; Throughput; cryptographic hash functions; gr⊘stl; interleaved and low area; sha-3;

fLanguage

English

Publisher

ieee

Conference_Titel

Open Source Systems and Technologies (ICOSST), 2012 International Conference on

Conference_Location

Lahore

Print_ISBN

978-1-4673-3094-7

Type

conf

DOI

10.1109/ICOSST.2012.6472835

Filename

6472835