Title :
Power-saving analysis of adiabatic logic in subthreshold region
Author :
Takahashi, Y. ; Sekine, Taku ; Nayan, N.A. ; Yokoyama, Masafumi
Author_Institution :
Dept. of Electr. & Electron., Gifu Univ., Gifu, Japan
Abstract :
This paper reports a comparison of energy dissipation between different adiabatic logics in the subthreshold operation. In SPICE simulation we use a real industrial 0.18 μm BSIM3v3 model having a device parameter in the subthreshold region and then confirm the energy savings of quasi-adiabatic logic families, namely, 2N2N2P, 2PC2AL, CAL, ECRL, PAL, PECRL, PFAL, and SAL. From the results we show that the energy consumption of our previously proposed 2PC2AL inverter is lower than those of the other adiabatic logics, in the range of from 10 kHz to 10 MHz.
Keywords :
CMOS logic circuits; logic gates; 2PC2AL; 2PC2AL inverter; CAL; ECRL; PAL; PECRL; PFAL; SAL; SPICE simulation; device parameter; efficient charge recovery logic; energy consumption; energy dissipation; energy savings; frequency 10 kHz to 10 MHz; p-type effective charge recovery logic; pass-transistor adiabatic logic; positive feedback adiabatic logic; power-saving analysis; predictive technology model; quasiadiabatic logic families; real-industrial BSIM3v3 model; size 0.18 mum; subthreshold region; two-phase clocked CMOS adiabatic logic; CMOS integrated circuits; Clocks; Energy dissipation; Inverters; Logic gates; Power supplies; Transistors; RFID; adiabatic logic; low power; smart card; subthreshold logic;
Conference_Titel :
Intelligent Signal Processing and Communications Systems (ISPACS), 2012 International Symposium on
Conference_Location :
New Taipei
Print_ISBN :
978-1-4673-5083-9
Electronic_ISBN :
978-1-4673-5081-5
DOI :
10.1109/ISPACS.2012.6473558
