A Current-Density Centric Logical Effort Delay and Power Model for High-Speed CML Gates

This paper presents a logical effort delay and power model for high-speed current-mode logic (CML) circuits. Current density centric and voltage swing dependent logical effort parameters are defined in terms of the characteristic current density for peak transistor cutoff frequency, which remains relatively constant across different technology nodes. Based on this model, constant and non-constant current density biasing schemes in data-paths of CML circuits are investigated and optimized for delay, power, and energy-delay metrics. The proposed model is simple yet sufficiently accurate for technology nodes in the constant-field scaling regime.