Transistor-level optimization of CMOS complex gates

Author

Possani, Vinicius N. ; Marques, Felipe S. ; da Rosa Junior, L.S. ; Callegaro, Vinicius ; Reis, Andre I. ; Ribas, Renato P.

Author_Institution

Group of Archit. & Integrated Circuits, Fed. Univ. of Pelotas - UFPel, Pelotas, Brazil

fYear

2013

fDate

Feb. 27 2013-March 1 2013

Firstpage

1

Lastpage

4

Abstract

This paper presents a new methodology to generate efficient transistor networks. Transistor-level optimization consists in an effective possibility to increase design quality when generating CMOS logic gates to be inserted in standard cell libraries. Starting from an input ISOP, the proposed method is able to deliver series-parallel and non-series-parallel arrangements with reduced transistor count. The experiments performed over the set of 4-input P-class Booleans functions have demonstrated the efficiency of the proposed approach.

Keywords

Boolean functions; CMOS logic circuits; integrated circuit design; logic design; logic gates; 4-input P-class Boolean function; CMOS complex gates; CMOS logic gates; design quality; input ISOP; series-parallel nonseries-parallel arrangements; standard cell libraries; transistor count reduction; transistor networks; transistor-level optimization; Boolean functions; Equations; Kernel; Logic gates; Optimization; Switches; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (LASCAS), 2013 IEEE Fourth Latin American Symposium on

Conference_Location

Cusco

Print_ISBN

978-1-4673-4897-3

Type

conf

DOI

10.1109/LASCAS.2013.6519029

Filename

6519029