A low-power configurable VLSI architecture for sum of absolute differences calculation

This paper presents a new configurable VLSI architecture for Sum of Absolutes Differences (SAD) calculation with pel decimation capabilities. It was also described a non-configurable architecture for comparison. The proposed SAD architecture as well as a non-configurable architecture were synthesized to both nominal and Low-Vdd/High-Vt versions of a commercial 90nm technology. Synthesis results demonstrated that the configurability comes at the cost of negligible area and power overhead. In addition, pel decimation improvements of up to 60% in latency and energy efficiency were observed. It was also observed that the configurable architecture benefit more from the Low-Vdd/High-Vt synthesis than the non-configurable architecture.