Non-stationary statistical simulation of blind-oversampling CDR circuits

Statistical approach is the only practical set of methods for reliable simulation of Clock and Data Recovery circuits which operate at low bit-error rates. The paper deals with a statistical simulation model for blind-oversampling CDR circuits, which estimate the center of the data eye by counting the edges in several subintervals that divide the signal period. In the steady-state, the process is described by the multinomial distribution. The developed model simulates the estimation process in the non-stationary case, which allows including sinusoidal jitter, and frequency offset. Some simulation results are presented.