DocumentCode :
601094
Title :
Formalism and reuse in NoC design
Author :
Escale, D.K.F.R. ; Ramos, K.D.N. ; Ribeiro, C.M.F.A.
Author_Institution :
Dept. of Comput., State of Univ. of Rio Grande do Norte, Natal, Brazil
fYear :
2013
fDate :
Feb. 27 2013-March 1 2013
Firstpage :
1
Lastpage :
4
Abstract :
This paper presents a formal approach to assist designers in the early stages of QoS-aware NoC design. Reuse of validated topologies and communication mechanism specifications are listed as a proposal benefit, which can potentially minimize risks and costs in the next steps of the process design, e.g. code generation and simulations. Additionally, qualitative analysis of essential project properties, mainly communication issues like latency and throughput, can be also achieved from formal specifications. Z notation was used as a formal description technique.
Keywords :
formal specification; integrated circuit design; network-on-chip; quality of service; QoS-aware NoC design; Z notation; code generation; communication mechanism specifications; formal description technique; formal specifications; network-on-chip design; process design; risk minimisation; validated topology reuse; Formal specifications; Measurement; Network topology; Quality of service; Routing; Throughput; Topology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (LASCAS), 2013 IEEE Fourth Latin American Symposium on
Conference_Location :
Cusco
Print_ISBN :
978-1-4673-4897-3
Type :
conf
DOI :
10.1109/LASCAS.2013.6519082
Filename :
6519082
Link To Document :
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